The present disclosure relates to semiconductor devices and methods for fabricating the semiconductor devices, and more particularly, to semiconductor devices which are formed by flip chip mounting with solder bumps and methods for fabricating the semiconductor devices.
In recent years, there has been an increasing demand for higher-performance and smaller-size electronic apparatuses, in which electronic parts need to be integrated and mounted with higher density. Semiconductor devices (semiconductor packages) used in such electronic apparatuses have had an increasingly smaller size and larger number of pins.
Conventional packages having a lead frame have reached the limit of their size reduction. Therefore, in order to increase the integration and mounting densities of a semiconductor device, wire bonding, tape automated bonding (TAB), or flip chip has been used for fabrication of the semiconductor device. Of these mounting techniques, flip chip can provide the highest density of a semiconductor device while reducing the size of the semiconductor device, and therefore, is frequently used for semiconductor devices for computer apparatuses, high-performance mobile apparatuses, etc.
Flip chip is a surface mounting technique which can provide a large number of electrical connections in a small area, but leads to a narrower pitch of connection pads as the size of a semiconductor device decreases and the number of pins in the semiconductor device increases. As the connection pad pitch is narrowed, the height of solder bumps tends to decrease. It is expected that, in the future, semiconductor devices having such a narrower connection pad pitch (particularly, 200 μm or less) will become a mainstream.
In a typical flip chip mounting, solder bumps are formed on electrode pads provided on a semiconductor chip with an under bump metal (UBM) layer being interposed as a barrier layer therebetween in order to reduce or prevent an intermetallic compound which would otherwise be formed of copper, aluminum or an alloy thereof contained in the electrode pad and tin contained in the solder bump.
Also, on the connection pad provided on an interconnect substrate on which the semiconductor chip is mounted, a barrier metal layer made of a metal, such as nickel (Ni), titanium (Ti), etc., or an alloy thereof is formed in order to reduce or prevent an alloy layer which would otherwise be formed of tin contained in the solder bump and copper contained in the connection pad, thereby improving the reliability of connection. Note that, in general, as the barrier metal layer, an electroless nickel film which is formed by electroless nickel plating is used from the standpoint of manufacturing cost and workability.
The semiconductor chip and the interconnect substrate have significantly different coefficients of thermal expansion. Therefore, if there is a large change in temperature of the semiconductor chip and the interconnect substrate during a flip chip mounting process etc., stress is concentrated and applied to portions of the solder bump which bonds the semiconductor chip to the interconnect substrate. In this case, a crack is likely to occur in the bonding portions or in the vicinity thereof, resulting in a faulty connection.
Therefore, in order to ensure the reliability of connection, the bonding portions of the solder bumps may be encapsulated by filling a gap between the semiconductor chip and the interconnect substrate with an insulating resin material called “underfill” and curing the material after flip chip mounting. In this case, however, as described above, in a semiconductor device which has a smaller size and a larger number of pins, the solder bump also has a smaller size, and therefore, stress applied to the bonding portion of the solder bump increases. Therefore, the protection by encapsulation of the bonding portion using the underfill resin material is unlikely to be sufficient for prevention of occurrence of a crack.
Various measures have been taken for the above problem. For example, Japanese Patent Publication No. 2007-242782 describes the following technique. In a semiconductor device in which solder bumps serving as electrodes for external connection are joined to a semiconductor substrate, a simple structure is provided which does not accompany an increase in thickness, and the volumes of solder bumps located on the four corner portions of the semiconductor chip to which stress is particularly concentrated and applied to are increased compared to the other solder bumps, whereby the cross-sectional areas of the solder bumps on the corner portions are increased.
Thus, in the semiconductor device described in Japanese Patent Publication No. 2007-242782, in order to improve the life of connection in a state in which the semiconductor chip is mounted on the interconnect substrate, the opening diameters of only electrode pads on the four corner portions of the semiconductor chip are increased compared to the other electrode pads formed on the semiconductor chip. As a result, solder bumps which are formed on the four corner portions of the semiconductor chip are larger than the other solder bumps, and the bonding portions of the solder bumps having the larger diameter can reduce or absorb stress.